diff --git a/systems/lctr-a9xx/patches/u-boot/patches-2013.01.01/99-igep0020-uart1-rs232.patch b/systems/lctr-a9xx/patches/u-boot/patches-2013.01.01/99-igep0020-uart1-rs232.patch deleted file mode 100644 index 188d948..0000000 --- a/systems/lctr-a9xx/patches/u-boot/patches-2013.01.01/99-igep0020-uart1-rs232.patch +++ /dev/null @@ -1,14 +0,0 @@ -diff -Nru u-boot-2013.01.01/board/isee/igep0020/igep0020.h u-boot-2013.01.01.rasm/board/isee/igep0020/igep0020.h ---- u-boot-2013.01.01/board/isee/igep0020/igep0020.h 2013-01-31 19:47:42.000000000 +0000 -+++ u-boot-2013.01.01.rasm/board/isee/igep0020/igep0020.h 2013-05-28 11:42:12.230996733 +0100 -@@ -132,6 +132,10 @@ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\ -+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ -+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ -+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ -+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\ diff --git a/systems/lctr-a9xx/patches/u-boot/patches-2014.01-rc3/00-igep0020-lsts.patch b/systems/lctr-a9xx/patches/u-boot/patches-2014.01-rc3/00-igep0020-lsts.patch new file mode 100644 index 0000000..8a41ae6 --- /dev/null +++ b/systems/lctr-a9xx/patches/u-boot/patches-2014.01-rc3/00-igep0020-lsts.patch @@ -0,0 +1,310 @@ +diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h +index 181f81f..d1320a1 100644 +--- a/board/isee/igep00x0/igep00x0.h ++++ b/board/isee/igep00x0/igep00x0.h +@@ -131,6 +131,10 @@ static void setup_net_chip(void); + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\ ++ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\ ++ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /* UART1_RTS */\ ++ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /* UART1_CTS */\ ++ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\ +@@ -145,6 +149,10 @@ static void setup_net_chip(void); + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\ ++ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /* McBSP2_FSX */\ ++ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /* McBSP2_CLKX */\ ++ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /* McBSP2_DR */\ ++ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /* McBSP2_DX */\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */ + #endif +diff --git a/boards.cfg b/boards.cfg +index a8336cc..bcc9bb2 100644 +--- a/boards.cfg ++++ b/boards.cfg +@@ -1246,3 +1246,4 @@ Orphan powerpc mpc8xx - - genietv + Orphan powerpc mpc8xx - - mbx8xx MBX - - + Orphan powerpc mpc8xx - - mbx8xx MBX860T - - + Orphan powerpc mpc8xx - - nx823 NX823 - - ++Active arm armv7 omap3 isee igep00x0 igep0020_lsts omap3_igep00x0_lsts:MACH_TYPE=MACH_TYPE_IGEP0020 Ricardo Martins +diff --git a/include/configs/omap3_igep00x0_lsts.h b/include/configs/omap3_igep00x0_lsts.h +new file mode 100644 +index 0000000..858261c +--- /dev/null ++++ b/include/configs/omap3_igep00x0_lsts.h +@@ -0,0 +1,269 @@ ++/* ++ * LSTS optimized configuration for IGEPv2 board ++ * ++ * (C) Copyright 2012 ++ * ISEE 2007 SL, ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __IGEP00X0_LSTS_H ++#define __IGEP00X0_LSTS_H ++ ++#include ++ ++/* ++ * Boot-delay. ++ */ ++#ifdef CONFIG_BOOTDELAY ++# undef CONFIG_BOOTDELAY ++#endif ++#define CONFIG_BOOTDELAY 0 ++#define CONFIG_ZERO_BOOTDELAY_CHECK 1 ++ ++/* ++ * High Level Configuration Options ++ */ ++#define CONFIG_OMAP 1 /* in a TI OMAP core */ ++#define CONFIG_OMAP34XX 1 /* which is a 34XX */ ++#define CONFIG_OMAP_GPIO ++#define CONFIG_OMAP_COMMON ++#define CONFIG_OMAP3_GPIO_3 ++ ++#define CONFIG_SDRC /* The chip has SDRC controller */ ++ ++#include ++#include ++#include ++ ++/* ++ * Display CPU and Board information ++ */ ++#define CONFIG_DISPLAY_CPUINFO 1 ++#define CONFIG_DISPLAY_BOARDINFO 1 ++ ++/* Clock Defines */ ++#define V_OSCK 26000000 /* Clock output from T2 */ ++#define V_SCLK (V_OSCK >> 1) ++ ++#define CONFIG_MISC_INIT_R ++ ++#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ ++#define CONFIG_SETUP_MEMORY_TAGS 1 ++#define CONFIG_INITRD_TAG 1 ++#define CONFIG_REVISION_TAG 1 ++ ++#define CONFIG_OF_LIBFDT ++ ++/* ++ * NS16550 Configuration ++ */ ++#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ ++#define CONFIG_SYS_NS16550 ++#define CONFIG_SYS_NS16550_SERIAL ++#define CONFIG_SYS_NS16550_REG_SIZE (-4) ++#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK ++ ++/* select serial console configuration */ ++#define CONFIG_CONS_INDEX 3 ++#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 ++#define CONFIG_SERIAL3 3 ++ ++/* allow to overwrite serial and ethaddr */ ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_SYS_BAUDRATE_TABLE {57600, 115200} ++#define CONFIG_GENERIC_MMC 1 ++#define CONFIG_MMC 1 ++#define CONFIG_OMAP_HSMMC 1 ++#define CONFIG_DOS_PARTITION 1 ++ ++#undef CONFIG_SHOW_BOOT_PROGRESS ++ ++/* commands to include */ ++#include ++ ++#define CONFIG_CMD_BOOTZ ++#define CONFIG_CMD_CACHE ++#define CONFIG_CMD_EXT4 ++#define CONFIG_CMD_FAT ++#define CONFIG_CMD_FS_GENERIC ++#define CONFIG_CMD_I2C ++#define CONFIG_CMD_MMC ++ ++#undef CONFIG_BOOTM_NETBSD ++#undef CONFIG_BOOTM_PLAN9 ++#undef CONFIG_BOOTM_RTEMS ++#undef CONFIG_BOOTM_VXWORKS ++#undef CONFIG_BOOTP_DNS ++#undef CONFIG_BOOTP_DNS2 ++#undef CONFIG_BOOTP_SEND_HOSTNAME ++#undef CONFIG_CMD_ASKENV ++#undef CONFIG_CMD_BDI ++#undef CONFIG_CMD_BOOTD ++#undef CONFIG_CMD_CRC32 ++#undef CONFIG_CMD_DFU ++#undef CONFIG_CMD_DHCP ++#undef CONFIG_CMD_EDITENV ++#undef CONFIG_CMD_EDITENV ++#undef CONFIG_CMD_EXPORTENV ++#undef CONFIG_CMD_FPGA ++#undef CONFIG_CMD_ITEST ++#undef CONFIG_CMD_LOADB ++#undef CONFIG_CMD_LOADS ++#undef CONFIG_CMD_MEMORY ++#undef CONFIG_CMD_MISC ++#undef CONFIG_CMD_NET ++#undef CONFIG_CMD_NFS ++#undef CONFIG_CMD_PING ++#undef CONFIG_CMD_SETGETDCR ++#undef CONFIG_CMD_SPI ++#undef CONFIG_MII ++#undef CONFIG_MUSB_GADGET ++#undef CONFIG_MUSB_HOST ++#undef CONFIG_NAND ++#undef CONFIG_OMAP3_SPI ++#undef CONFIG_SPI ++#undef CONFIG_SPI_BOOT ++#undef CONFIG_SPL_ETH_SUPPORT ++#undef CONFIG_SPL_NAND_LOAD ++#undef CONFIG_SPL_NAND_SUPPORT ++#undef CONFIG_SPL_SPI_FLASH_SUPPORT ++#undef CONFIG_SPL_SPI_LOAD ++#undef CONFIG_SPL_SPI_SUPPORT ++#undef CONFIG_SPL_YMODEM_SUPPORT ++#undef CONFIG_SYS_LONGHELP ++#undef CONFIG_FLASH_CFI_DRIVER ++#undef CONFIG_FLASH_CFI_MTD ++#undef CONFIG_CMD_FLASH ++#undef CONFIG_CMD_SAVEENV ++#undef CONFIG_CMD_IMPORTENV ++#undef CONFIG_CMD_IMLS ++#undef CONFIG_CMD_IMI ++ ++/* Environment. */ ++#define CONFIG_ENV_SIZE (128 << 10) ++#define CONFIG_ENV_IS_NOWHERE ++ ++/* ++ * TWL4030 ++ */ ++#define CONFIG_TWL4030_POWER 1 ++ ++#ifndef CONFIG_SPL_BUILD ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "loadaddr=0x80200000\0" \ ++ "dtbaddr=0x81600000\0" \ ++ "ipaddr=192.168.1.90\0" \ ++ "serverip=192.168.1.147\0" \ ++ "ethaddr=00:50:da:4b:5a:67\0" \ ++ "console=ttyO2,115200n8\0" \ ++ "mmcroot=/dev/mmcblk0p2\0" \ ++ "mmcrootfstype=ext4\0" ++ ++#define CONFIG_BOOTCOMMAND \ ++ "setenv bootargs \"console=${console} root=${mmcroot} rootfstype=${mmcrootfstype} rootwait ro quiet\"; " \ ++ "mmc dev 0; " \ ++ "ext4load mmc0 0:2 ${loadaddr} /boot/kernel; " \ ++ "ext4load mmc0 0:2 ${dtbaddr} /boot/board.dtb; " \ ++ "bootz ${loadaddr} - ${dtbaddr}; " ++ ++#endif ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#ifdef CONFIG_SYS_LONGHELP ++# undef CONFIG_SYS_LONGHELP ++#endif ++ ++#define CONFIG_SYS_NO_FLASH ++#define CONFIG_SYS_I2C ++#define CONFIG_SYS_I2C_OMAP34XX ++#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 ++#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 ++#define CONFIG_SYS_HUSH_PARSER ++#define CONFIG_SYS_PROMPT "U-Boot # " ++#define CONFIG_SYS_CBSIZE 256 ++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) ++#define CONFIG_SYS_MAXARGS 16 ++#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) ++#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) ++#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000) /* 31MB */ ++#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) ++#define CONFIG_SYS_MONITOR_LEN (256 << 10) ++ ++/* ++ * OMAP3 has 12 GP timers, they can be driven by the system clock ++ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). ++ * This rate is divided by a local divisor. ++ */ ++#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) ++#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ ++ ++/* ++ * Physical Memory Map ++ */ ++#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ ++#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 ++#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 ++ ++/* ++ * Size of malloc() pool ++ */ ++#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) ++ ++/* ++ * SMSC911x Ethernet ++ */ ++#if defined(CONFIG_CMD_NET) ++# define CONFIG_SMC911X ++# define CONFIG_SMC911X_32_BIT ++# define CONFIG_SMC911X_BASE 0x2C000000 ++#endif /* (CONFIG_CMD_NET) */ ++ ++/* ++ * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader ++ * and older u-boot.bin with the new U-Boot SPL. ++ */ ++#define CONFIG_SYS_TEXT_BASE 0x80008000 ++#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 ++#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 ++#define CONFIG_SYS_INIT_RAM_SIZE 0x800 ++#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ ++ CONFIG_SYS_INIT_RAM_SIZE - \ ++ GENERATED_GBL_DATA_SIZE) ++ ++/* SPL */ ++#define CONFIG_SPL ++#define CONFIG_SPL_FRAMEWORK ++#define CONFIG_SPL_NAND_SIMPLE ++#define CONFIG_SPL_TEXT_BASE 0x40200800 ++#define CONFIG_SPL_MAX_SIZE (54 * 1024) ++#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK ++ ++/* move malloc and bss high to prevent clashing with the main image */ ++#define CONFIG_SYS_SPL_MALLOC_START 0x87000000 ++#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 ++#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */ ++#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ ++ ++/* MMC boot config */ ++#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ ++#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ ++#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 ++#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" ++ ++#define CONFIG_SPL_BOARD_INIT ++#define CONFIG_SPL_LIBCOMMON_SUPPORT ++#define CONFIG_SPL_LIBDISK_SUPPORT ++#define CONFIG_SPL_I2C_SUPPORT ++#define CONFIG_SPL_LIBGENERIC_SUPPORT ++#define CONFIG_SPL_MMC_SUPPORT ++#define CONFIG_SPL_FAT_SUPPORT ++#define CONFIG_SPL_SERIAL_SUPPORT ++ ++#define CONFIG_SPL_POWER_SUPPORT ++#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" ++ ++#endif /* __IGEP00X0_LSTS_H */