diff --git a/systems/lctr-a9xx/cfg/linux-3.14.57.cfg b/systems/lctr-a9xx/cfg/linux-3.14.57.cfg
index 378176e..372ee35 100644
--- a/systems/lctr-a9xx/cfg/linux-3.14.57.cfg
+++ b/systems/lctr-a9xx/cfg/linux-3.14.57.cfg
@@ -1,6 +1,6 @@
 #
 # Automatically generated file; DO NOT EDIT.
-# Linux/arm 3.14.16 Kernel Configuration
+# Linux/arm 3.14.57 Kernel Configuration
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -1245,7 +1245,7 @@ CONFIG_PINCTRL=y
 CONFIG_PINMUX=y
 CONFIG_PINCONF=y
 CONFIG_GENERIC_PINCONF=y
-# CONFIG_DEBUG_PINCTRL is not set
+CONFIG_DEBUG_PINCTRL=y
 # CONFIG_PINCTRL_CAPRI is not set
 # CONFIG_PINCTRL_MSM8X74 is not set
 CONFIG_PINCTRL_SINGLE=y
diff --git a/systems/lctr-a9xx/patches/u-boot/2014.07/00-igep0020-lsts.patch b/systems/lctr-a9xx/patches/u-boot/2014.07/00-igep0020-lsts.patch
index 8540fd0..23bed24 100644
--- a/systems/lctr-a9xx/patches/u-boot/2014.07/00-igep0020-lsts.patch
+++ b/systems/lctr-a9xx/patches/u-boot/2014.07/00-igep0020-lsts.patch
@@ -2,16 +2,16 @@ diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h
 index 181f81f..fe643e4 100644
 --- a/board/isee/igep00x0/igep00x0.h
 +++ b/board/isee/igep00x0/igep00x0.h
-@@ -146,7 +146,19 @@ static void setup_net_chip(void);
+@@ -146,5 +146,17 @@ static void setup_net_chip(void);
  	MUX_VAL(CP(SYS_BOOT5),      (IEN  | PTD | DIS | M4)) /* GPIO_7 */\
  	MUX_VAL(CP(SYS_BOOT6),      (IEN  | PTD | DIS | M4)) /* GPIO_8 */\
  	MUX_VAL(CP(SDRC_CKE0),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE0 */\
 -	MUX_VAL(CP(SDRC_CKE1),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE1 */
 +	MUX_VAL(CP(SDRC_CKE1),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE1 */\
-+	MUX_VAL(CP(UART1_TX),       (IDIS | PTD | DIS | M0)) /* UART1_TX */\
-+	MUX_VAL(CP(UART1_RTS),      (IEN  | PTD | DIS | M4)) /* UART1_RTS */\
-+	MUX_VAL(CP(UART1_CTS),      (IEN  | PTU | DIS | M4)) /* UART1_CTS */\
-+	MUX_VAL(CP(UART1_RX),       (IEN  | PTD | DIS | M0)) /* UART1_RX */\
++	MUX_VAL(CP(UART1_TX),       (IDIS | PTD | DIS | M2)) /* UART1_TX */\
++	MUX_VAL(CP(UART1_RTS),      (IEN  | PTD | EN  | M7)) /* UART1_RTS */\
++	MUX_VAL(CP(UART1_CTS),      (IEN  | PTD | EN  | M7)) /* UART1_CTS */\
++	MUX_VAL(CP(UART1_RX),       (IEN  | PTD | DIS | M2)) /* UART1_RX */\
 +	MUX_VAL(CP(MMC2_DAT1),      (IDIS | PTD | DIS | M4)) /* GPIO_133 */\
 +	MUX_VAL(CP(MMC2_DAT3),      (IDIS | PTD | DIS | M4)) /* GPIO_135 */\
 +	MUX_VAL(CP(MCBSP1_FSR),     (IEN  | PTD | DIS | M4)) /* GPIO_157 */\