311 lines
11 KiB
Diff
311 lines
11 KiB
Diff
diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h
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index 181f81f..d1320a1 100644
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--- a/board/isee/igep00x0/igep00x0.h
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+++ b/board/isee/igep00x0/igep00x0.h
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@@ -131,6 +131,10 @@ static void setup_net_chip(void);
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MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
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MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
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MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
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+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
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+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /* UART1_RTS */\
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+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /* UART1_CTS */\
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+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\
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MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
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MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
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MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
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@@ -145,6 +149,10 @@ static void setup_net_chip(void);
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MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
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MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
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MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
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+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /* McBSP2_FSX */\
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+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /* McBSP2_CLKX */\
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+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /* McBSP2_DR */\
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+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /* McBSP2_DX */\
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MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
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MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */
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#endif
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diff --git a/boards.cfg b/boards.cfg
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index a8336cc..bcc9bb2 100644
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--- a/boards.cfg
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+++ b/boards.cfg
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@@ -1246,3 +1246,4 @@ Orphan powerpc mpc8xx - - genietv
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Orphan powerpc mpc8xx - - mbx8xx MBX - -
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Orphan powerpc mpc8xx - - mbx8xx MBX860T - -
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Orphan powerpc mpc8xx - - nx823 NX823 - -
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+Active arm armv7 omap3 isee igep00x0 igep0020_lsts omap3_igep00x0_lsts:MACH_TYPE=MACH_TYPE_IGEP0020 Ricardo Martins <rasm@fe.up.pt>
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diff --git a/include/configs/omap3_igep00x0_lsts.h b/include/configs/omap3_igep00x0_lsts.h
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new file mode 100644
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index 0000000..858261c
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--- /dev/null
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+++ b/include/configs/omap3_igep00x0_lsts.h
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@@ -0,0 +1,269 @@
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+/*
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+ * LSTS optimized configuration for IGEPv2 board
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+ *
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+ * (C) Copyright 2012
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+ * ISEE 2007 SL, <www.iseebcn.com>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#ifndef __IGEP00X0_LSTS_H
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+#define __IGEP00X0_LSTS_H
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+
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+#include <asm/sizes.h>
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+
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+/*
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+ * Boot-delay.
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+ */
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+#ifdef CONFIG_BOOTDELAY
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+# undef CONFIG_BOOTDELAY
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+#endif
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+#define CONFIG_BOOTDELAY 0
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+#define CONFIG_ZERO_BOOTDELAY_CHECK 1
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+
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+/*
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+ * High Level Configuration Options
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+ */
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+#define CONFIG_OMAP 1 /* in a TI OMAP core */
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+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
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+#define CONFIG_OMAP_GPIO
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+#define CONFIG_OMAP_COMMON
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+#define CONFIG_OMAP3_GPIO_3
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+
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+#define CONFIG_SDRC /* The chip has SDRC controller */
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+
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+#include <asm/arch/cpu.h>
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+#include <asm/arch/omap3.h>
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+#include <asm/mach-types.h>
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+
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+/*
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+ * Display CPU and Board information
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+ */
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+#define CONFIG_DISPLAY_CPUINFO 1
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+#define CONFIG_DISPLAY_BOARDINFO 1
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+
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+/* Clock Defines */
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+#define V_OSCK 26000000 /* Clock output from T2 */
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+#define V_SCLK (V_OSCK >> 1)
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+
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+#define CONFIG_MISC_INIT_R
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+
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+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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+#define CONFIG_SETUP_MEMORY_TAGS 1
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+#define CONFIG_INITRD_TAG 1
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+#define CONFIG_REVISION_TAG 1
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+
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+#define CONFIG_OF_LIBFDT
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+
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+/*
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+ * NS16550 Configuration
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+ */
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+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
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+#define CONFIG_SYS_NS16550
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+#define CONFIG_SYS_NS16550_SERIAL
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+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
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+
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+/* select serial console configuration */
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+#define CONFIG_CONS_INDEX 3
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+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
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+#define CONFIG_SERIAL3 3
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+
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+/* allow to overwrite serial and ethaddr */
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+#define CONFIG_ENV_OVERWRITE
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+#define CONFIG_BAUDRATE 115200
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+#define CONFIG_SYS_BAUDRATE_TABLE {57600, 115200}
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+#define CONFIG_GENERIC_MMC 1
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+#define CONFIG_MMC 1
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+#define CONFIG_OMAP_HSMMC 1
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+#define CONFIG_DOS_PARTITION 1
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+
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+#undef CONFIG_SHOW_BOOT_PROGRESS
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+
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+/* commands to include */
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+#include <config_cmd_default.h>
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+
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+#define CONFIG_CMD_BOOTZ
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+#define CONFIG_CMD_CACHE
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+#define CONFIG_CMD_EXT4
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+#define CONFIG_CMD_FAT
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+#define CONFIG_CMD_FS_GENERIC
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+#define CONFIG_CMD_I2C
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+#define CONFIG_CMD_MMC
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+
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+#undef CONFIG_BOOTM_NETBSD
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+#undef CONFIG_BOOTM_PLAN9
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+#undef CONFIG_BOOTM_RTEMS
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+#undef CONFIG_BOOTM_VXWORKS
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+#undef CONFIG_BOOTP_DNS
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+#undef CONFIG_BOOTP_DNS2
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+#undef CONFIG_BOOTP_SEND_HOSTNAME
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+#undef CONFIG_CMD_ASKENV
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+#undef CONFIG_CMD_BDI
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+#undef CONFIG_CMD_BOOTD
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+#undef CONFIG_CMD_CRC32
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+#undef CONFIG_CMD_DFU
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+#undef CONFIG_CMD_DHCP
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+#undef CONFIG_CMD_EDITENV
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+#undef CONFIG_CMD_EDITENV
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+#undef CONFIG_CMD_EXPORTENV
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+#undef CONFIG_CMD_FPGA
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+#undef CONFIG_CMD_ITEST
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+#undef CONFIG_CMD_LOADB
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+#undef CONFIG_CMD_LOADS
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+#undef CONFIG_CMD_MEMORY
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+#undef CONFIG_CMD_MISC
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+#undef CONFIG_CMD_NET
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+#undef CONFIG_CMD_NFS
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+#undef CONFIG_CMD_PING
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+#undef CONFIG_CMD_SETGETDCR
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+#undef CONFIG_CMD_SPI
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+#undef CONFIG_MII
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+#undef CONFIG_MUSB_GADGET
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+#undef CONFIG_MUSB_HOST
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+#undef CONFIG_NAND
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+#undef CONFIG_OMAP3_SPI
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+#undef CONFIG_SPI
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+#undef CONFIG_SPI_BOOT
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+#undef CONFIG_SPL_ETH_SUPPORT
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+#undef CONFIG_SPL_NAND_LOAD
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+#undef CONFIG_SPL_NAND_SUPPORT
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+#undef CONFIG_SPL_SPI_FLASH_SUPPORT
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+#undef CONFIG_SPL_SPI_LOAD
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+#undef CONFIG_SPL_SPI_SUPPORT
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+#undef CONFIG_SPL_YMODEM_SUPPORT
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+#undef CONFIG_SYS_LONGHELP
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+#undef CONFIG_FLASH_CFI_DRIVER
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+#undef CONFIG_FLASH_CFI_MTD
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+#undef CONFIG_CMD_FLASH
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+#undef CONFIG_CMD_SAVEENV
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+#undef CONFIG_CMD_IMPORTENV
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+#undef CONFIG_CMD_IMLS
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+#undef CONFIG_CMD_IMI
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+
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+/* Environment. */
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+#define CONFIG_ENV_SIZE (128 << 10)
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+#define CONFIG_ENV_IS_NOWHERE
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+
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+/*
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+ * TWL4030
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+ */
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+#define CONFIG_TWL4030_POWER 1
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+
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+#ifndef CONFIG_SPL_BUILD
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+#define CONFIG_EXTRA_ENV_SETTINGS \
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+ "loadaddr=0x80200000\0" \
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+ "dtbaddr=0x81600000\0" \
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+ "ipaddr=192.168.1.90\0" \
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+ "serverip=192.168.1.147\0" \
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+ "ethaddr=00:50:da:4b:5a:67\0" \
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+ "console=ttyO2,115200n8\0" \
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+ "mmcroot=/dev/mmcblk0p2\0" \
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+ "mmcrootfstype=ext4\0"
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+
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+#define CONFIG_BOOTCOMMAND \
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+ "setenv bootargs \"console=${console} root=${mmcroot} rootfstype=${mmcrootfstype} rootwait ro quiet\"; " \
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+ "mmc dev 0; " \
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+ "ext4load mmc0 0:2 ${loadaddr} /boot/kernel; " \
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+ "ext4load mmc0 0:2 ${dtbaddr} /boot/board.dtb; " \
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+ "bootz ${loadaddr} - ${dtbaddr}; "
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+
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+#endif
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+
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+/*
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+ * Miscellaneous configurable options
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+ */
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+#ifdef CONFIG_SYS_LONGHELP
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+# undef CONFIG_SYS_LONGHELP
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+#endif
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+
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+#define CONFIG_SYS_NO_FLASH
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+#define CONFIG_SYS_I2C
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+#define CONFIG_SYS_I2C_OMAP34XX
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+#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
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+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
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+#define CONFIG_SYS_HUSH_PARSER
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+#define CONFIG_SYS_PROMPT "U-Boot # "
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+#define CONFIG_SYS_CBSIZE 256
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+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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+#define CONFIG_SYS_MAXARGS 16
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+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
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+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000) /* 31MB */
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+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
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+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
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+
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+/*
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+ * OMAP3 has 12 GP timers, they can be driven by the system clock
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+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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+ * This rate is divided by a local divisor.
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+ */
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+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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+
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+/*
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+ * Physical Memory Map
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+ */
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+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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+
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+/*
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+ * Size of malloc() pool
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+ */
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+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
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+
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+/*
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+ * SMSC911x Ethernet
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+ */
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+#if defined(CONFIG_CMD_NET)
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+# define CONFIG_SMC911X
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+# define CONFIG_SMC911X_32_BIT
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+# define CONFIG_SMC911X_BASE 0x2C000000
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+#endif /* (CONFIG_CMD_NET) */
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+
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+/*
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+ * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
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+ * and older u-boot.bin with the new U-Boot SPL.
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+ */
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+#define CONFIG_SYS_TEXT_BASE 0x80008000
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+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
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+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
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+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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+ CONFIG_SYS_INIT_RAM_SIZE - \
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+ GENERATED_GBL_DATA_SIZE)
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+
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+/* SPL */
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+#define CONFIG_SPL
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+#define CONFIG_SPL_FRAMEWORK
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+#define CONFIG_SPL_NAND_SIMPLE
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+#define CONFIG_SPL_TEXT_BASE 0x40200800
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+#define CONFIG_SPL_MAX_SIZE (54 * 1024)
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+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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+
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+/* move malloc and bss high to prevent clashing with the main image */
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+#define CONFIG_SYS_SPL_MALLOC_START 0x87000000
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+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
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+#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */
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+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
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+
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+/* MMC boot config */
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+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
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+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
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+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
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+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
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+
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+#define CONFIG_SPL_BOARD_INIT
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+#define CONFIG_SPL_LIBCOMMON_SUPPORT
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+#define CONFIG_SPL_LIBDISK_SUPPORT
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+#define CONFIG_SPL_I2C_SUPPORT
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+#define CONFIG_SPL_LIBGENERIC_SUPPORT
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+#define CONFIG_SPL_MMC_SUPPORT
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+#define CONFIG_SPL_FAT_SUPPORT
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+#define CONFIG_SPL_SERIAL_SUPPORT
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+
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+#define CONFIG_SPL_POWER_SUPPORT
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+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
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+
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+#endif /* __IGEP00X0_LSTS_H */
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