support smoothing on atom counting nodes (beta)
This commit is contained in:
Tiago Gomes
@@ -23,6 +23,10 @@ AndNode::weight (void) const
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stack<pair<unsigned, unsigned>> SetOrNode::nrGrsStack;
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double
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SetOrNode::weight (void) const
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{
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@@ -583,82 +587,195 @@ LiftedCircuit::shatterCountedLogVarsAux (
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TinySet<LiteralId>
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LogVarTypes
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unionTypes (const LogVarTypes& types1, const LogVarTypes& types2)
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{
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if (types1.empty()) {
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return types2;
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}
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if (types2.empty()) {
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return types1;
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}
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assert (types1.size() == types2.size());
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LogVarTypes res;
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for (size_t i = 0; i < types1.size(); i++) {
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if (types1[i] == LogVarType::POS_LV
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&& types2[i] == LogVarType::POS_LV) {
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res.push_back (LogVarType::POS_LV);
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} else if (types1[i] == LogVarType::NEG_LV
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&& types2[i] == LogVarType::NEG_LV) {
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res.push_back (LogVarType::NEG_LV);
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} else {
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res.push_back (LogVarType::FULL_LV);
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}
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}
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return res;
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}
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vector<LogVarTypes>
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getAllPossibleTypes (unsigned nrLogVars)
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{
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if (nrLogVars == 0) {
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return {};
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}
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if (nrLogVars == 1) {
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return {{LogVarType::POS_LV},{LogVarType::NEG_LV}};
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}
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vector<LogVarTypes> res;
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Indexer indexer (vector<unsigned> (nrLogVars, 2));
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while (indexer.valid()) {
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LogVarTypes types;
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for (size_t i = 0; i < nrLogVars; i++) {
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if (indexer[i] == 0) {
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types.push_back (LogVarType::POS_LV);
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} else {
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types.push_back (LogVarType::NEG_LV);
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}
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}
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res.push_back (types);
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++ indexer;
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}
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return res;
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}
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bool
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containsTypes (const LogVarTypes& typesA, const LogVarTypes& typesB)
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{
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for (size_t i = 0; i < typesA.size(); i++) {
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if (typesA[i] == LogVarType::FULL_LV) {
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} else if (typesA[i] == LogVarType::POS_LV
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&& typesB[i] == LogVarType::POS_LV) {
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} else if (typesA[i] == LogVarType::NEG_LV
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&& typesB[i] == LogVarType::NEG_LV) {
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} else {
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return false;
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}
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}
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return true;
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}
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LitLvTypesSet
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LiftedCircuit::smoothCircuit (CircuitNode* node)
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{
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assert (node != 0);
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TinySet<LiteralId> propagatingLids;
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LitLvTypesSet propagLits;
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switch (getCircuitNodeType (node)) {
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case CircuitNodeType::OR_NODE: {
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OrNode* casted = dynamic_cast<OrNode*>(node);
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TinySet<LiteralId> lids1 = smoothCircuit (*casted->leftBranch());
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TinySet<LiteralId> lids2 = smoothCircuit (*casted->rightBranch());
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TinySet<LiteralId> missingLeft = lids2 - lids1;
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TinySet<LiteralId> missingRight = lids1 - lids2;
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LitLvTypesSet lids1 = smoothCircuit (*casted->leftBranch());
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LitLvTypesSet lids2 = smoothCircuit (*casted->rightBranch());
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LitLvTypesSet missingLeft = lids2 - lids1;
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LitLvTypesSet missingRight = lids1 - lids2;
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createSmoothNode (missingLeft, casted->leftBranch());
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createSmoothNode (missingRight, casted->rightBranch());
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propagatingLids |= lids1;
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propagatingLids |= lids2;
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propagLits |= lids1;
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propagLits |= lids2;
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break;
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}
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case CircuitNodeType::AND_NODE: {
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AndNode* casted = dynamic_cast<AndNode*>(node);
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TinySet<LiteralId> lids1 = smoothCircuit (*casted->leftBranch());
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TinySet<LiteralId> lids2 = smoothCircuit (*casted->rightBranch());
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propagatingLids |= lids1;
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propagatingLids |= lids2;
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LitLvTypesSet lids1 = smoothCircuit (*casted->leftBranch());
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LitLvTypesSet lids2 = smoothCircuit (*casted->rightBranch());
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propagLits |= lids1;
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propagLits |= lids2;
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break;
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}
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case CircuitNodeType::SET_OR_NODE: {
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// TODO
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SetOrNode* casted = dynamic_cast<SetOrNode*>(node);
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propagLits = smoothCircuit (*casted->follow());
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TinySet<pair<LiteralId,unsigned>> litSet;
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for (size_t i = 0; i < propagLits.size(); i++) {
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litSet.insert (make_pair (propagLits[i].lid(),
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propagLits[i].logVarTypes().size()));
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}
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LitLvTypesSet missingLids;
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for (size_t i = 0; i < litSet.size(); i++) {
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vector<LogVarTypes> allTypes = getAllPossibleTypes (litSet[i].second);
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for (size_t j = 0; j < allTypes.size(); j++) {
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bool typeFound = false;
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for (size_t k = 0; k < propagLits.size(); k++) {
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if (litSet[i].first == propagLits[k].lid()
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&& containsTypes (allTypes[j], propagLits[k].logVarTypes())) {
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typeFound = true;
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break;
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}
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}
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if (typeFound == false) {
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missingLids.insert (LiteralLvTypes (litSet[i].first, allTypes[j]));
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}
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}
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}
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createSmoothNode (missingLids, casted->follow());
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// TODO change propagLits to full lvs
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break;
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}
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case CircuitNodeType::SET_AND_NODE: {
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SetAndNode* casted = dynamic_cast<SetAndNode*>(node);
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propagatingLids = smoothCircuit (*casted->follow());
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propagLits = smoothCircuit (*casted->follow());
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break;
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}
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case CircuitNodeType::INC_EXC_NODE: {
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IncExcNode* casted = dynamic_cast<IncExcNode*>(node);
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TinySet<LiteralId> lids1 = smoothCircuit (*casted->plus1Branch());
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TinySet<LiteralId> lids2 = smoothCircuit (*casted->plus2Branch());
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TinySet<LiteralId> missingPlus1 = lids2 - lids1;
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TinySet<LiteralId> missingPlus2 = lids1 - lids2;
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LitLvTypesSet lids1 = smoothCircuit (*casted->plus1Branch());
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LitLvTypesSet lids2 = smoothCircuit (*casted->plus2Branch());
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LitLvTypesSet missingPlus1 = lids2 - lids1;
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LitLvTypesSet missingPlus2 = lids1 - lids2;
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createSmoothNode (missingPlus1, casted->plus1Branch());
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createSmoothNode (missingPlus2, casted->plus2Branch());
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propagatingLids |= lids1;
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propagatingLids |= lids2;
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propagLits |= lids1;
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propagLits |= lids2;
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break;
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}
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case CircuitNodeType::LEAF_NODE: {
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propagatingLids.insert (node->clauses()[0].literals()[0].lid());
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propagLits.insert (LiteralLvTypes (
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node->clauses()[0].literals()[0].lid(),
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node->clauses()[0].logVarTypes(0)));
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}
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default:
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break;
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}
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return propagatingLids;
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return propagLits;
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}
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void
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LiftedCircuit::createSmoothNode (
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const TinySet<LiteralId>& missingLids,
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const LitLvTypesSet& missingLits,
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CircuitNode** prev)
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{
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if (missingLids.empty() == false) {
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if (missingLits.empty() == false) {
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Clauses clauses;
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for (size_t i = 0; i < missingLids.size(); i++) {
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Clause c = lwcnf_->createClauseForLiteral (missingLids[i]);
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for (size_t i = 0; i < missingLits.size(); i++) {
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LiteralId lid = missingLits[i].lid();
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const LogVarTypes& types = missingLits[i].logVarTypes();
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Clause c = lwcnf_->createClauseForLiteral (lid);
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for (size_t j = 0; j < types.size(); j++) {
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LogVar X = c.literals().front().logVars()[j];
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if (types[j] == LogVarType::POS_LV) {
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c.addPositiveCountedLogVar (X);
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} else if (types[j] == LogVarType::NEG_LV) {
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c.addNegativeCountedLogVar (X);
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}
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}
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c.addAndNegateLiteral (c.literals()[0]);
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clauses.push_back (c);
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}
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