e5f4633c39
which included commits to RCS files with non-trunk default branches. git-svn-id: https://yap.svn.sf.net/svnroot/yap/trunk@5 b08c6af1-5177-4d33-ba66-4b1c6b8b522a
314 lines
10 KiB
Plaintext
314 lines
10 KiB
Plaintext
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/*
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**********************************************************************
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*
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* CLP(R) Version 2.0 (Example Programs Release)
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* (C) Copyright, March 1986, Monash University
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*
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**********************************************************************
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*/
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%
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% Transistor amplifier design and analysis package.
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% The goal
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% ?- go1.
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% analyses an existing amplifier circuit, while the goal
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% ?- go2.
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% imposes certain design constraints on an amplifier of
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% a certain form and then determines suitable component values,
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% by choosing them from a list of available (preffered) components.
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%
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/****************************************************************************/
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/* Major goals */
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/****************************************************************************/
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dc_analysis(Vcc1,Vcc2,Circuit):-
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solve_dc(mean,Circuit ,[n(cc1,Vcc1,[_]),n(cc2,Vcc2,[_]),n(gnd,0,[_])],
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Nodelist,Collector_Currents),
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current_solve(Nodelist),
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print_value(Nodelist),
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print_circuit(Circuit).
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full_analysis(Vcc1,Vcc2,Circuit,In,Out,Type,Stability,Gain,Inresist,Outresist):-
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Inresist = -1 / Iin,
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Gain = Vout,
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Outresist = -1 / Iout,
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circuit(Vcc1, Vcc2, Circuit,In, Out,Type),
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solve_dc(mean,Circuit ,[n(cc1,Vcc1,[_]), n(cc2,Vcc2,[_]), n(gnd,0,[_])],
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Nodelist,Collector_Currents),
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current_solve(Nodelist),
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%print_value(Nodelist),
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stability(Vcc1,Vcc2,Circuit,Collector_Currents,Stability),
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printf("Stab %\n",[Stability]),
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solve_ss(Circuit,Collector_Currents,
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[n(cc1,0,[_]),n(cc2,0,[_]),n(gnd,0,[_]),
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n(In,1,[Iin]),n(Out,Vout,[])],Nodelist2),
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current_solve(Nodelist2),
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%print_value(Nodelist2),
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solve_ss(Circuit,Collector_Currents,
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[n(cc1,0,[_]),n(cc2,0,[_]),n(gnd,0,[_]),
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n(Out,1,[Iout])],Nodelist3),
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%print_value(Nodelist3),
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current_solve(Nodelist3),
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%print_value(Nodelist3),
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printf("Outresist % \n",[Outresist]),
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print_circuit(Circuit).
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/****************************************************************************/
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/* small signal equivalent solve */
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/****************************************************************************/
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solve_ss([],[], List,List).
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solve_ss([[Component,_,Data,Points]|Rest],CCin,Innodes,Outnodes):-
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connecting(Points,Volts,Amps,Innodes,Tmpnodes),
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component_ss(Component,Data,Volts,Amps,CCin,CCout),
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solve_ss(Rest,CCout,Tmpnodes,Outnodes).
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component_ss(resistor,R,[V1,V2],[I,-1*I],Cc,Cc):-
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V1-V2 = R*I,
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resistor_val(R).
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component_ss(capacitor,_,[V,V],[I,-1*I],Cc,Cc).
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component_ss(transistor,[npn,Code,active],[Vb,Vc,Ve], [Ib,Ic,Ie],[Icol|CC],CC):-
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Vb - Ve = (Beta * Vt / Icol) * Ib,
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Ic = Beta * Ib,
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Ie + Ic + Ib = 0,
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transistor_type(Type,Code,Beta,_,_,Vt,mean).
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/****************************************************************************/
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/* dc component solving */
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/****************************************************************************/
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solve_dc(_, [], List, List, []).
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solve_dc(Kind,[[Component,_,Data,Points] | Rest], Inlist,Outlist,CCin):-
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connecting(Points, Volts, Amps, Inlist,Tmplist),
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component_dc(Component,Data,Volts,Amps,CCin,CCout,Kind),
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solve_dc(Kind, Rest, Tmplist,Outlist,CCout).
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component_dc(resistor,R,[V1,V2],[I,-1*I],Cc,Cc,_):-
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V1-V2 = R*I,
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resistor_val(R).
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component_dc(capacitor,_,[V1,V2],[0,0],Cc,Cc,_).
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component_dc(transistor,[Type,Code,State],Volts, [Ib,Ic,Ie],[Ic|CC],CC,Kind):-
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transistor_type(Type,Code,Beta,Vbe,Vcesat,_,Kind),
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transistor_state(Type,State,Beta,Vbe,Vcesat,Volts,[Ib,Ic,Ie]).
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component_dc(diode,[Code,State],Volts,Amps,Cc,Cc,_):-
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diode_type(Code,Vf,Vbreak),
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diode_state(State,Vf,Vreak,Volts,Amps).
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/****************************************************************************/
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/* diode and transistor states / and relationships */
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/****************************************************************************/
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diode_state(forward,Vf,Vbreak,[Vp,Vm],[I, -1*I]):-
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/* forward biased */
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Vp - Vm = Vf,
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I >= 0.
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diode_state(reverse,Vf,Vbreak,[Vp,Vm],[I, -1*I]):-
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/* reverse biased */
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Vp - Vm < Vf,
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Vm - Vp < Vbreak,
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I = 0.
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transistor_state(npn, active, Beta, Vbe,_,[Vb, Vc, Ve], [Ib, Ic, Ie]):-
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Vb = Ve + Vbe,
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Vc >= Vb,
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Ib >= 0,
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Ic = Beta*Ib,
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Ie+Ib+Ic = 0.
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transistor_state(pnp, active, Beta, Vbe,_,[Vb, Vc, Ve], [Ib, Ic, Ie]):-
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Vb = Ve + Vbe,
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Vc <= Vb,
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Ib <= 0,
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Ic = Beta*Ib,
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Ie+Ib+Ic = 0.
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transistor_state(npn, saturated, Beta, Vbe, Vcesat,[Vb, Vc, Ve], [Ib, Ic, Ie]):-
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Vb = Ve + Vbe,
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Vc = Ve + Vcesat,
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Ib >= 0,
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Ic >= 0,
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Ie+Ib+Ic = 0.
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transistor_state(pnp, saturated, Beta, Vbe, Vcesat,[Vb, Vc, Ve], [Ib, Ic, Ie]):-
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Vb = Ve + Vbe,
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Vc = Ve + Vcesat,
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Ib <= 0,
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Ic <= 0,
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Ie+Ib+Ic = 0.
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transistor_state(npn, cutoff, Beta, Vbe, Vcesat,[Vb, Vc, Ve], [Ib, Ic, Ie]):-
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Vb <= Ve + Vbe,
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Ib = 0,
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Ic = 0,
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Ie = 0.
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transistor_state(pnp, cutoff, Beta, Vbe, Vcesat,[Vb, Vc, Ve], [Ib, Ic, Ie]):-
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Vb >= Ve + Vbe,
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Ib = 0,
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Ic = 0,
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Ie = 0.
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/****************************************************************************/
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/* connecting components routines */
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/****************************************************************************/
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connecting([],[],[],List,List).
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connecting([P|PR],[V|VR],[I|IR], Inlist,Outlist):-
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connect(P,V,I,Inlist,Tmplist),
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connecting(PR,VR,IR,Tmplist,Outlist).
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connect(P,V,I,[],[n(P,V,[I])]):-!.
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connect(P,V,I, [n(P,V,Ilist) | Rest],[n(P,V,[I|Ilist])|Rest]):-!.
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connect(P,V,I, [A|Rest], [A|Newrest]) :-
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connect(P,V,I, Rest, Newrest).
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/****************************************************************************/
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/* Stability Analysis */
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/****************************************************************************/
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stability(Vcc1,Vcc2,Circuit, CollectorCurrents, Stability):-
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solve_dc(minn,Circuit ,[n(cc1,Vcc1,[_]),n(cc2,Vcc2,[_]),n(gnd,0,[_])],
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Nodelist1,MinCurrents),
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current_solve(Nodelist1),
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% printf(" Min %\n Minmodes \n",[MinCurrents]),
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% print_value(Nodelist1),
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solve_dc(maxx,Circuit ,[n(cc1,Vcc1,[_]),n(cc2,Vcc2,[_]),n(gnd,0,[_])],
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Nodelist2,MaxCurrents),
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current_solve(Nodelist2),
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% printf(" Max %\n Maxnodes\n",[MaxCurrents]),
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% print_value(Nodelist2),
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calculate(MinCurrents,MaxCurrents,CollectorCurrents,Stability).
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calculate(MinCurrents,MaxCurrents,CollectorCurrents,Stability):-
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cal(MinCurrents,MaxCurrents,CollectorCurrents,Percents),
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% printf(" Percent % \n",[Percents]),
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maxi(Percents,0,Stability).
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cal([Min|Rin],[Max|Rax],[Ic|Rc],[Pc|Rpc]):-
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Pc=max(Ic-Min,Max-Ic),
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cal(Rin,Rax,Rc,Rpc).
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cal([],[],[],[]).
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maxi([N1|R],N2,P):-
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M=max(N1,N2),
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maxi(R,M,P).
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maxi([],P,P).
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/****************************************************************************/
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/* Miscellaneous things */
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/****************************************************************************/
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current_solve([]).
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current_solve([n(_,_,L) | Rest]) :-
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kcl(L),
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current_solve(Rest).
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print_value([]).
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print_value([n(P,V,I) | Rest]) :-
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printf("% at % %\n",[P,V,I]),
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print_value(Rest).
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print_circuit([]).
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print_circuit([[Comp,Name,Data,Points] | Rest]) :-
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printf(" % at % %\n",[Comp,Name,Data]),
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print_circuit(Rest).
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sum([X|T],Z) :-
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X+P = Z,
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sum(T,P).
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sum([],0).
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kcl(L) :-
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sum(L,0).
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/****************************************************************************/
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/* Database of circuits and components */
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/****************************************************************************/
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resistor_val(100).
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resistor_val(50).
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resistor_val(27).
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resistor_val(5).
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resistor_val(2).
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resistor_val(1).
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diode_type(di1, 0.6, 100).
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transistor_type(npn, tr0, 100, 0.7, 0.3, 0.025,mean).
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transistor_type(npn, tr0, 50, 0.8, 0.3, 0.025,minn).
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transistor_type(npn, tr0, 150, 0.6, 0.3, 0.025,maxx).
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transistor_type(pnp, tr1, 100, -0.7, -0.3, 0.025,mean).
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transistor_type(pnp, tr1, 50, -0.8, -0.3, 0.025,minn).
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transistor_type(pnp, tr1, 150, -0.6, -0.3, 0.025,maxx).
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circuit(15,0,[
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[capacitor,c1,c1,[in,b]],
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[resistor,r1,R1,[b,cc1]],
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[resistor,r2,R2,[b,gnd]],
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[transistor,tr,[npn,tr0,active],[b,c,e]],
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[resistor,re,Re,[e,gnd]],
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[capacitor,c2,c2,[c,out]],
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[resistor,rc,Rc,[c,cc1]],
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[capacitor,c3,c3,[e,gnd]]],
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in,out,common_emitter).
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circuit(15,0,[
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[capacitor,c1,C1,[gnd,b]],
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[resistor,r1,R1,[b,cc1]],
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[resistor,r2,R2,[b,gnd]],
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[transistor,tr,[pnp,tr1,active],[b,c,e]],
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[resistor,re,Re,[e,gnd]],
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[capacitor,c2,C2,[c,in]],
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[resistor,rc,Rc,[c,cc1]],
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[capacitor,c3,C3,[e,out]]],
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in,out,common_base).
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circuit(15,0,[
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[capacitor,c1,C1,[in,b]],
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[resistor,r1,R1,[b,cc1]],
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[resistor,r2,R2,[b,gnd]],
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[transistor,tr,[npn,tr0,active],[b,cc1,e]],
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[resistor,re,Re,[e,gnd]],
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[capacitor,c3,C3,[e,out]]],
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in,out,emitter_follower).
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go1:- dc_analysis(15,-12,[
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[diode,d1,[di1,St1],[a,gnd]],
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[diode,d2,[di1,St2],[a,cc1]],
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[resistor,r1,100,[a,cc1]],
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[diode,d3,[di1,St3],[a,p1]],
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[diode,d4,[di1,St4],[p1,b]],
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[resistor,r2,100,[b,cc2]],
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[transistor,tr,[npn,tr0,State],[b,c,gnd]],
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[resistor,rc,100,[c,cc1]]]).
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% Answer:
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% cc1 at 15 [0, 0.144, 0, -0.144]
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% cc2 at -12 [-0.114, 0.114]
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% gnd at 0 [0, -0.03, 0.03]
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% a at 0.6 [0.114, -0.144, 0, 0.03]
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% p1 at 0 [0.114, -0.114]
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% b at -0.6 [0, 0.114, -0.114]
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% c at 15 [0, 0]
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% diode at d1 [di1, forward]
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% diode at d2 [di1, reverse]
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% resistor at r1 100
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% diode at d3 [di1, forward]
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% diode at d4 [di1, forward]
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% resistor at r2 100
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% transistor at tr [npn, tr0, cutoff]
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% resistor at rc 100
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go2:-
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Vcc = 15, Stability < 0.5, Gain > 0.5,
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Inresistance >= 25, Outresistance <= 2,
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full_analysis(Vcc, _, Circuit, _, _, emitter_follower, Stability,
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Gain, Inresistance, Outresistance),
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write(Circuit),nl.
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% Answer:
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% Stab 0.001947
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% Outresist 0.857107
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% capacitor at c1 Data_48
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% resistor at r1 100
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% resistor at r2 100
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% transistor at tr [npn, tr0, active]
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% resistor at re 100
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% capacitor at c3 Data_52
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% [[capacitor, c1, C1_48, [in, b]], [resistor, r1, 100, [b, cc1]],
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% [resistor, r2, 100, [b, gnd]], [transistor, tr, [npn, tr0, active],
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% [b, cc1, e]], [resistor, re, 100, [e, gnd]], [capacitor, c3, C3_52,
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% [e, out]]]
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?- printf("\n>>> Sample goals: go1/0, go2/0\n", []).
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